Programmable logic devices (PLDs) (e.g., field programmable gate arrays (FPGAs), complex programmable logic devices (CPLDs), field programmable systems on a chip (FPSCs), or other types of programmable devices) may be configured with various user designs to implement desired functionality. Typically, the user designs are synthesized and mapped into configurable resources (e.g., programmable logic gates, look-up tables (LUTs), embedded hardware, or other types of resources) and interconnections available in particular PLDs. Physical placement and routing for the synthesized and mapped user designs may then be determined to generate configuration data for the particular PLDs.
PLDs are commonly used to deserialize serialized input data streams, and, as a result, are often implemented with a limited number of dedicated deserializer blocks that can be used to recover or extract serialized data from input data streams. However, such blocks require significant area in order to be implemented in a PLD, and there are correspondingly limited routing resources that can be used to implement user designs incorporating such dedicated deserializer blocks. Moreover, such blocks often employ a phase locked loop or an accurate clock to oversample the data stream, which can present a significant timing burden on general routing and, in particular, clock-related circuitry, all of which can be in limited supply in a relatively inexpensive PLD. Such constraints can severely limit the scope of user designs that can be implemented in PLDs, can result in degraded PLD performance, and can significantly increase the time and processing resources needed to determine connection routings for the PLD.
Embodiments of the present disclosure and their advantages are best understood by referring to the detailed description that follows. It should be appreciated that like reference numerals are used to identify like elements illustrated in one or more of the figures.